Cross Coupled nand-gate has a leaking current?

[patato]

Dear all,
i have build a cross coupled circuit for my compator, just like the one in the fig.
here's my problem:

i've run dc analysis
when the input (i.e latch_p and latch_n) is at the state of (3.3V, 0v) or (0V, 3.3V),
the circuit works fine.

but when the input is (0,0), which should be the hold state, the output(Q) is neither at 3.3v nor 0v, it's at a strange voltage of 1.57V!
and a large current flows from VDDA,through M5 M9 and M4,to VSSA.

Can any1 help me figure this out? it's giving me headache for a while,
and this does cause a problem where i need to put all the circuit into a power-down mode.

 

[Fom]

give a pulse on Latch_P or Latch_N. Everything will be OK.

 

[patato]

give a pulse on Latch_P or Latch_N. Everything will be OK.

i've done that in .tran simulation,it did work.
but i can't do that in .dc analysis, and in a power down mode,there shouldn't be a pulse at input.

well actually it can be fixed by modifying the latch, i simply don't know why there's a steady op point between 3.3 and 0 at the output.
It's a positive feedback structure isn't it? i thought the output must be at 0 or VDDA.

still, thanks for your reply!

 

[Fom]

There is three DC solutions 0, VDDA and middle point. But middle point is not a stable solution. In real world the small deviation from this point will force voltages to VDDA or 0. But DC analysis considers an ideal case. So it prefers the middle poin solution. You can insert a VDC with smal DC voltage connected to one of the latch input. Or introduce some assimetry into latch.