Critical path (Xilinx ISE)

[spman]

Hi

How can find the critical path that is preventing clock constraint to be met? I use Xilinx ISE.

 

[moottii]

You have all of your delays in synthesis report.

 

[spman]

You have all of your delays in synthesis report.

Synthesis report or place and route report? I found information about delays in place and route report. But I don't know how it is useful. How should exploit it?

Thanks

 

[moottii]

There is a small part in synthesis report called "Timing Report".
You can find them there.

 

[ads_ee]

Read up on using trce.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/isehelp_start.htm#pta_c_overview.htm

This tool will show you the timing violations and the entire path delays.