Creating schematic from Verilog in cadence

[awais107]

Hi

I want to create schematic of a verilog file in cadence. My goal is to simulate verilog file in cadence ADE-XL using ADC and DAC. But, when i make a verilog file (of simple 8 bit adder) and its symbol in cadence, its netlist don't get generated at simulation level and i get an error.

 

[Dominik Przyborowski]

You should synthesize verilog file in rc-compiler and then import a new verilog file with physical gates into virtuoso.

 

[awais107]

You should synthesize verilog file in rc-compiler and then import a new verilog file with physical gates into virtuoso.

Thanks. But after synthesize how can i make symbol and link with my schematic. (how to call it in the virtuoso)

Also, is there any way to verify the behavioral working in virtuoso using ADE-XL from verilog code

Thanks

- - - Updated - - -

Thanks. But after synthesize how can i make symbol and link with my schematic. (how to call it in the virtuoso)

Also, is there any way to verify the behavioral working in virtuoso using ADE-XL from verilog code

Thanks

I tried to add the synthesize version but still getting the same error:

Loading seCore.cxt
\o Begin Incremental Netlisting Mar 10 00:16:53 2014
\o ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
\o instance 'I11' in cell 'Test_SUM'. Either add one of these views to the library 'A_AFE_F',
\o cell 'A_ADD_8' or modify the view list to contain an existing view.
\o
\o End netlisting Mar 10 00:16:53 2014
\o ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.
\o ...unsuccessful.
\e *Error* Error during netlisting of design for the point ID (5 1).
\e ("error" 0 t nil ("*Error* "))

 

[dick_freebird]

I've tried this and found the created schematic a nearly
useless, unreadable mess.


Now, I do not see verilog (different than veriloga) in your
view-list. But an analog simulator is not going to switch into
digital views usefully anyway. The mixed signal setup involves
partitioning and somebody somewhere has to insert all of the
digital<>analog widgets (forget the proper name) at the
seams. I think you want to go back and look at mixed signal
options, partitioning.

Or you might try instead to convert a verilog block to veriloga
which the simulator -will- digest more natively. That might be
as low-touch as wrapping the pin voltage / current inputs and
outputs around the digital code block. I dunno.

 

[Dominik Przyborowski]

If You want to simulate Your verilog design in spectre on transistor level, You have to synthesize your code into verilog code containing standard cells and import from virtuoso icfb menu into one of Your virtuoso library. After import this synthesized code You are able to see typical virtuoso cell with symbol and schematic views.

 

[awais107]

If You want to simulate Your verilog design in spectre on transistor level, You have to synthesize your code into verilog code containing standard cells and import from virtuoso icfb menu into one of Your virtuoso library. After import this synthesized code You are able to see typical virtuoso cell with symbol and schematic views.

I want to first verify the behavioral level working in the virtuoso. Can i do that ? Without synthesizing.

I tried to make a schematic symbol of verilog code (behavioral level) and was still getting the same error.

- - - Updated - - -

I've tried this and found the created schematic a nearly
useless, unreadable mess.


Now, I do not see verilog (different than veriloga) in your
view-list. But an analog simulator is not going to switch into
digital views usefully anyway. The mixed signal setup involves
partitioning and somebody somewhere has to insert all of the
digital<>analog widgets (forget the proper name) at the
seams. I think you want to go back and look at mixed signal
options, partitioning.

Or you might try instead to convert a verilog block to veriloga
which the simulator -will- digest more natively. That might be
as low-touch as wrapping the pin voltage / current inputs and
outputs around the digital code block. I dunno.

Thanks. But do you have any idea of converting verilog into verilogA using which simulator? (Can i do on virtuoso)