Hi All
would anyone be able to help me out, or point me in the right direction of some documentation for this, i have searched the web and read through xilinx documents but cant seem to find an answer:
i have a project for targer XC9500 series CPLD, has top level shematic and a pin.ucf file. in order not to clutter up my only schematic i opened/created a new .sch file (test1.sch) and built some logic (PISO shift register) in it, named the I/O lines, i have created a symbol (called it "PISO") and attached it to this schematic. everything ok. i have created an library and included this symbol. Now, i have added this symbol "PISO" to my schematic in my project and wired it up:
now my Design hierarchy is looking like the below figure:
the "orange question mark" means what exactly?
when i go to synthesize the top model i get the error:
im obviously missing some step between creating my symbol "PISO" and it being usefull to another project file. could anyone help me out on this? thanks in advance!