Create test vectors from real world signals

matrixofdynamism · May 9, 2017

What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?

ads-ee · May 9, 2017

I think this can output VHDL/Verilog for timing diagrams https://www.syncad.com/waveform_translator.htm. There was also another program that was supposed to be able to produce testbenches for waveforms, but I can't recall what the software was called.

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never mind it's on the same website https://www.syncad.com/testbencher_verilog_vhdl_testbench_generator.htm. This is probably what you would want to get.

ThisIsNotSam · May 9, 2017

matrixofdynamism said:
What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?

can your scope dump information into a file (CSV-like, maybe?) ? I would write a testbench that parses the scope output file and makes a simulation environment out of it.

ads-ee · May 9, 2017

ThisIsNotSam said:
can your scope dump information into a file (CSV-like, maybe?) ? I would write a testbench that parses the scope output file and makes a simulation environment out of it.

Funny you should mention this...I'm doing that right now in my current testbench

Not for the timing but it's got my data in it.

Create test vectors from real world signals

matrixofdynamism

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Create test vectors from real world signals

matrixofdynamism

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