Is there any algorithm or key points for creating an EM substrate? Or is it only possible to change the substrate parameters and simulate a very large number of times until an acceptable result is obtained? only a brute-force search?)
In other words, there is no clear answer and I have to rely only on my own experience?
The agreement on SRF is indeep unexpected, that should agree much better. Capacitance for SRF is a combination of C between the turns and C to the substrate below.
One possible issue for C between the turns is modelling of the top layer passivation: if you have thick top metal and assume that these conductors are fully embedded in dielectric (=planar stackup modelling) that will over-estimate C if real passivation is conformal with much air between the traces. Not sure about CMOS, but in SiGe I often see those thick top metals (some microns).
~~
To check C to the substrate, you can model a large square plate, with port reference at bottom of the substrate, and compared results to the shunt C specification in process spec. That will give an idea if your stackup is correct for shunt C.
~~
Sometimes measurements are not correct, so try to double check that also. Having some error in shunt C is not unusual, even if on-wafer-cal was done.
~~
For effective permittivity, calculation depends on direction also. I have attached my calculations below:
View attachment 175001
~~
The appnote on via merging was created when ADS had no built-in via array merging. Today, the recommended method is to use ADS via array merging.
View attachment 175000
--- Updated ---
I have created many EM stackups for RFIC technology and my advice is: use data from process specification. It is very dangerous to tweak values for agreement between EM and measurement. There are too many error sources in measurement, and user generated modelling error in EM, so you will never get reliable stackups that way. If there is one thing that you can trust, it is the process documentation.
Would it be possible to change the capacitance at this place if the dielectric layers at this place were set very thin or with a very low dielectric value?
Right now I have the total thickness between Al and M7 (0,5 + 0,035 + 0,6 + 0,04) - In order to place the MIM capacitor there.The combined case with/without MIM is difficult to configure indeed. For a layer-oriented planar solver like Momentum, such non-planar structures are difficult to capture.
I would propably keep it simple and create a stackup without MIM first. That should model your inductor case and many other cases, except the special cases MIM and pad open area.
Regarding SRF, check if your stackup models the conformal coating for thick Al layer properly. If that coating is thin in reality, just a conformal coating above the Al layer, you must NOT model this as Al layer fully embedded in that dielectric. Instead, I recommend to calculate an effective permittivity then, which is valid in horizontal direction between the inductor turns for your actual gap width in this inductor. Does SRF agree better now?
~~
I don't understand this part of your question. Do you mean an equivalent material to mimic the MIM, or what does this refer to ?
If I make the thicknesses of these dielectric layers very thin (~0.01 um for example) will this help to reduce the "extra" capacitance, and get a better SRF match?
I think this picture is as similar as possible to what I have in the DRMUltra thin layers can lead to numerical issues.
Not sure if I understand your technology correctly. Is the "normal" case in the inductor trace region to have some distance between M7 and Al, and "pad open" creates a connection similar to a via?
~~
As mentioned before, you have embedded the Al layer completely into oxide: oxide thickness is 0.5 + 2.93µm, and that also covers the gaps between turns am layer Al. In reality, there are gaps with air, and you over-estimate capacitance.
Let me use a picture from another technology, to explain what I mean:
View attachment 175017
Not sure if PadOpen layer can be considered - as metal layer over M7 or as Via between Al and M7?
Let's do some math: we have 45GHz SRF at 600pH inductance. I calculate parallel C as 21fF from these values.Or is this normal for the L-2L deembedding method ?
I would model that as a via, to connect Al and M7. Layer Al and M7 separated by 640nm oxide then, as shown in your cross section.
(We don't include the "valley" in Al at PadOpen then, but that's not an issue)
Let's do some math: we have 45GHz SRF at 600pH inductance. I calculate parallel C as 21fF from these values.
For measurements from clients, I have seen measurement uncertainty in shunt C of several fF per port. That would be enough to explain SRF shifts as you have observed.
But I really can't discuss more details, because that stuff is under NDA and because I'm not an expert in these on-wafer measurements.
--- Updated ---
~~
I think you better remove the detailed cross section from your last post, to avoid NDA trouble with the foundry.
I would model that as a via, to connect Al and M7. Layer Al and M7 separated by 640nm oxide then, as shown in your cross section.
(We don't include the "valley" in Al at PadOpen then, but that's not an issue)
Let's do some math: we have 45GHz SRF at 600pH inductance. I calculate parallel C as 21fF from these values.
For measurements from clients, I have seen measurement uncertainty in shunt C of several fF per port. That would be enough to explain SRF shifts as you have observed.
But I really can't discuss more details, because that stuff is under NDA and because I'm not an expert in these on-wafer measurements.
--- Updated ---
~~
I think you better remove the detailed cross section from your last post, to avoid NDA trouble with the foundry.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?