CRC Error insertion and detection

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rrucha

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Hello,

I have the auto generated CRC parallel verilog code for muti-bit data stream. I even wrote a testbench to check the CRC. Now I want to write a testbench that injects random errors and detects it. How can i do that in verilog?
 

you can use the force command in the simulator or the verilog version of force
 

ThisIsNotSam said:
you can use the force command in the simulator or the verilog version of force
Click to expand...

How will I detect it? Do I need to make the testbench such that it will emulate the receiver (receive the appended message, divide it by the polynomial and check if final answer is 0). So I will randomly inject errors and also check for it?
 

rrucha said:
How will I detect it? Do I need to make the testbench such that it will emulate the receiver (receive the appended message, divide it by the polynomial and check if final answer is 0). So I will randomly inject errors and also check for it?
Click to expand...

it's probably easier to have two instances of the design, one that you insert errors and one that you don't. provide the same inputs and see if the outputs match.
 

ThisIsNotSam said:
it's probably easier to have two instances of the design, one that you insert errors and one that you don't. provide the same inputs and see if the outputs match.
Click to expand...

So what you are saying is, 1. Check the CRC for a message without error 2. Check the CRC for a message with error. See if CRC1=CRC2; which they obviously wont be. And since the CRC with an injected error does not match the original CRC, there is an error in the message. Am I right? No need to emulate the receiver.
 

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