Hi,
I am wonder if is possible for a CPLD to write the status of a register in an external serial rom, and after a power cycle to retrieve the status of register.
If possible, is there a report on net to help me?
You mean serial EEPROM? Your CPLD needs to implement a serial interface controller, either SPI or I2C, to communicate with the memory device. Possible if your CPLD has sufficient free logic cells available.
Some CPLD have built-in user memory, e.g. Intel MAX V.
@FvM
Thank you.
I did not even know about their existence. In my mind I only had the MAX 10 fpga series.
I work with isp 4000V series from Lattice which have 5V I/O tolerance. I hope the same is true in Intel max, using only a resistor as they say in their site...
Unlike isp 4000V, MAX V (and it's predecessor MAX II) are not 5V tolerant. Some devices expose PCI clamp diodes that keep the input voltage within maximum ratings, but the diodes are programmable and not active during power-up. Thus I would prefer external voltage dividers for 5V input signals.
Unlike isp 4000V, MAX V (and it's predecessor MAX II) are not 5V tolerant. Some devices expose PCI clamp diodes that keep the input voltage within maximum ratings, but the diodes are programmable and not active during power-up. Thus I would prefer external voltage dividers for 5V input signals.
One needs to read device specification.
* some just say "abs max input voltage range", then a simple series resistor is not allowed.
* others add a note to the above statement "or current limited to xxx uA", then series reistors are allowed.
Current limits apply for devices with input clamp diodes. Neither isp 4000V nor MAX V devices have permanent clamp diodes, but isp 4000V has higher voltage rating (older technology), thus it's 5V tolerant.
Most vendors have stopped making 5V tolerant CPLD since long. Newer devices have even problems with excessive overshoot in the 3.3V domain. Main reason is the transition to nm IC processes.