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CPLD or FPGA design???

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555lin

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Guys, i have the task of designing a device for coupling
a DVI connector such as a video card DVI output with
a fiber optic cable at the transmitter side and the reverse
thing at the receiver side, so to say, a DVI optical extension.
To achieve that I have to transform a differential signalling at
the output of DVI (in TDMS format) into a form suitable for
driving an optical transmitter (0,+V).
Is there any way to solve the issue with a CPLD or FPGA or what???
 

kishore2k4

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Assuming single-link DVI, the maximum frequency to be supported is 165Mhz. That translates to, 165Mhz*24bits/pixel + blanking information = ~4Gbps

What you can do is either use the SerDes(RocketIO in the case of Xilinx) module in FPGAs or use off-the-shelf one's from TI etc to drive the optical PHY interface.
 

ameed

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hi all,

if you are to choose bettween cpld and fpga:?:

better to choose fpga kit.

and search on altera.com and xillinx.com.

thanx....
 

555lin

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What kind of module from TI is suitable
for such kind of an application?
 

kishore2k4

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555lin said:
What kind of module from TI is suitable
for such kind of an application?
http://focus.ti.com/paramsearch/doc...log&familyId=553&uiTemplateId=NODE_STRY_PGE_T

http://focus.ti.com/paramsearch/doc...log&familyId=551&uiTemplateId=NODE_STRY_PGE_T

Since I've no idea about your electronics background, let me explain a little about how the whole thing should work.

Your FPGA will have serial-to-parallel converters that basically convert the DVI serial data into parallel data. Then you'll simply switch each one of the parallel register(s) into the SerDes which takes care of the rest. The same thing happens in reverse on the other end. If you happened to get 24bit SerDes then everything is almost glueless or else there will be a delay in reconstructing the RGB signals at the other end.

Or you can use your own multiplexing strategy to switch a signle bit of each color so that there will be minimum delay.
 

    555lin

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shield

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It's depending on your cost margin and size of logics. In general, little logic use th cpld, others using the FPGA
 

cheggy

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Sure, U can do that with FPGA!
 

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