CPLD and JTAG connection

[sadashiv_sm]

port_en xilinx

Hi,

I have made a jatag cable for the xilinx cpld Xpla 3 familey as per xilinx circuit.
I have a cpld XCR3064XL-PC44.
I have connected the jtag pins and the VCC and GND pinsto the cpld .
the cpld works at 3.3v.

but my webpack dosent identify the jtag.
what will be the problem. I am searching for the solution. but if someone knows then let me know.

I havent connected PORT_EN pin. Its floating. what abt the clk pins,do i have to connect CLK pins .

waiting for reply....

Thanks and Regards....

Sadashiv...

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what we know is handful but what we dont know is oceanful..........
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[tlp71@hotmail.com]

jtag pins are not for use.
They are fixed from Xilinx, you can't map as others pins.
You can leave unconnected or (i think better ) refer at vcc or GND (according whit data shhet specifications)
Bye.
G.

 

[sadashiv_sm]

hi,
Thanks for the kind reply.....

see my problem is .....
my xilxn ISE Webpack dosent detect the Jtag .....

I have done following things.....
I want to download a simple counter file into CPLD.
I have made the JTAG...and also connected to the jtag pins of CPLD to this circuit....and i have powered the CPLD with 3.3v regulated supply.

I havent connected any clk i.e. CLK and PORT_EN pins are floating....

if sombody has gone through the same situation or sombody has the solution for this please let me know....

Thanks and Regards...

Sadashiv

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What we know is handful what we dont know is oceanful.......
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[Buriedcode]

hey, here's my two cents (well, pennies at least)

So you've got your chip, powered, all pins floating apart from JTAG, download software for use with DL cable and of course you DL cable.

I haven't ever used Xilinx stuff, lattice have got me by the short and curly's (I have about 40 of their chips), so I can't give real advice, just some generic stuff.

Assuming you are using a parallel port cable:

1. Does your Download software allow you to pick diffirent types of cable? Lattice have named theirs, but there should be a 'generic serial' one.

2. When you say 'it doesn't detect it' does it simpley say something like 'no cable detected', or is it 'no power to cable'? Becuase the lattice cable has a 'Voltage detect' which must be tied to VCC for the software to detect it (think its pin 15 on the parallel cable). Also, some pins on the parallel cable must be tied together so the software knows that it is plugged in and not another parallel port thing. Something like pin 8 tied to 11 and 12.

3. Assuming you built the cable yourself, remember, even if you've wired up the buffer chip wrong, as long as you have the right connections to the parallel port connector, and you have a decent 3.3v powersupply to run it all, you will probably get something. It won't download, but it should detect it, then you can worry about debugging.

Sorry if this seems obvious, but we've all been stumped by something like having no power connected. Both cpld AND cable require power, even if you don't use a buffer chip (which you will for 3.3v, sometimes not for 5v).

As I said, I'm unfamiliar with Xilinx's stuff, so I could be a bit 'west' on this one. Try not connecting the CPLD to the Jtag cable, any different error messages?

Lastly, just googled 'xilinx download cable schematic' and there are loads, all pretty similar, maybe try a different one as some are as old as 1996, and the newer software might use slightly different pins on the parallel port.

Maybe it'll help, maybe it won't, but I'm bored and I know how frustrating it can be getting these things to work.

Good luck,

Buried(in)code.

 

[System.out]

IIRC Xilinx datasheet tells about conecting PORT_EN to GND with an 10K impedance for noisy environments, if you are not using these pins as I/O. Maybe that is your problem.

Good luck !

 

[issaiass]

If you want to make a fast jtag test use directly

TMS, TDI, TDO, TCK, GND, VCC to the parallel port of the PC and make sure a PullUp resistor is on TDO pin.