Hi,
One voltage signal running in parallel with clock signal.Here,how the switching clock signal affects the voltage signal in capacitive coupling mode...??
What's the mystery here?
You have an "aggressor" (clock) with an intrinsic impedance
(R, L, Ccouple) and you have a "victim" (shunt C, mostly).
You could set up a simple SPICE simulation and observe the
effect as a function of coupling capacitance (parallel length
and separation) and driving impedance (MOSFET and trace).
At low coupling C you will see edge "glitches" and at higher C
you may see the square wave at increasingly high amplitudes.
Victim shunt C (and R if any) will dilute the injected noise.
Clock coupling can also make deterministic jitter on near-aligned
data signals and product clocks (have seen co-routed 60MHz
and 90MHz clocks "chest-bump" each other every other cycle)
when coincident, anti-coincident edges speed up or slow down
a transition (in this case, who is the victim and who is the
aggressor, or both just come out bloody?).