counter value detection using edges

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ssudhasa

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Hi
I have problem:

question:
4 bit binary counter(0 to 3) , counts increments from 0 to 15 in clock A domain.
now the count has to be communicated in the other clock domain clock B using edge detection circuits.

what will be the ciruit will it use to detect count 2-3 . &
what will be the ciruit will it use to detect count 15-0 .


options are:

(1) four bit counter (clockA)--> bit(2) OR GATE bit(3) ---> negative edge detection circuit --> 4 bit counter (clock B)

(2) four bit counter (clockA)--> bit(2) OR GATE bit(3) ---> positive edge detection circuit --> 4 bit counter (clock B)

Thanks in advance.
 

I don't clearly see, what you want to achieve. In the general case, a consistent transfer of counter values across clock domain boundaries requires gray encoding, typically used e.g. in FIFO designs.
 

Hi,

Thanks for the reply.

My question is :
if i have to communicate the count of the 4 bit counter to the other clock domain, the domain.
the follong circuit is correct for 15-0 detection
OR it should be posed detection at the AND GATE .
 

What do you exactly mean with communicate the count? To signal the overflow, b3 negedge is sufficient, what's the purpose of b2?
 

okay ! that is for 15 --> 0 detection.

BUT for count 2-3 ?

0000
0001
0010 2
0011 3
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
 

Apparently, it's impossible by evaluating only two bits.
 

Thanks for the discussion.

I agree, you r right.
 

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