AbinayaSivam
Member level 1
Hello,
I am trying to implement counter module using MM-FIFO and to read the data in NIOS.
1. Enabling the counter from [1-bit PIO out (SOPC)]
2. Compiled Verilog code (counter), and created as a Symbol file (counter)
3. Interconnected counter module and Qsys component
4. To read data from NIOS
ISSUE: In Nios, I am getting all data "Zero`s". Please anyone guide me what is the problem in my code and design. I am stuck in this work for nearly 15 days:-x
Counter Code
Block design
NIOS CONSOLE
I am trying to implement counter module using MM-FIFO and to read the data in NIOS.
1. Enabling the counter from [1-bit PIO out (SOPC)]
2. Compiled Verilog code (counter), and created as a Symbol file (counter)
3. Interconnected counter module and Qsys component
4. To read data from NIOS
ISSUE: In Nios, I am getting all data "Zero`s". Please anyone guide me what is the problem in my code and design. I am stuck in this work for nearly 15 days:-x
Counter Code
Code:
module Counter(
input clk,
input enable,
input reset,
output reg[31:0] Final_value,
output reg trig
);
reg[31:0] counter_out;
reg [7:0] temp=0;
reg [31:0] counter_result;
wire temp1;
wire temp2;
always@(posedge clk)
begin
if(reset)
begin
trig<=0;
temp<=0;
counter_out<=0;
end
else if (enable==1'b1)
begin
counter_out<=counter_out+1;
temp<=temp+1;
if(temp==25)
begin
temp<=0;
trig<=~trig;
end
end
end
assign temp1=trig;
assign temp2=temp1&&clk;
always@(posedge temp2)
if(reset)
counter_result<=0;
else
begin
counter_result<=counter_result+1;
end
always@(posedge trig)
if(reset)
Final_value<=0;
else
begin
Final_value<=counter_result;
end
endmoduleBlock design
NIOS CONSOLE