Counter design problem !

[hillten]

Hi ! I am Hillten.

I want to design a large counter and it is compose from small counters (like 4-bit).

And I use two of the 4-bit counter, use first counter’s carry signal to enable next counter. But why it was increase at next clock. Please help me, Thanks!

The document is the simulation waveform and source code.

 

[nand_gates]

Generate carry one clk before will solve ur problem!
Here is an example...

module counter (
   // Outputs
   count, cy,
   // Inputs
   clk, reset_n, en
   );
   input clk, reset_n;
   input en;
   output [7:0] count;
   output       cy;
   count4 count4_0 (
                    // Outputs
                    .count              (count[3:0]),
                    .cy                 (cy_int),
                    // Inputs
                    .clk                (clk),
                    .reset_n            (reset_n),
                    .en                 (1'b1));
   count4 count4_1 (
                    // Outputs
                    .count              (count[7:4]),
                    .cy                 (cy),
                    // Inputs
                    .clk                (clk),
                    .reset_n            (reset_n),
                    .en                 (cy_int));   
endmodule // counter


module count4 (
   // Outputs
   count, cy,
   // Inputs
   clk, reset_n, en
   );
   input clk, reset_n;
   input en;
   output [3:0] count;
   output       cy;
   
   reg [3:0] count;
   assign    cy = &count;
   
   always @(posedge clk or negedge reset_n) begin
      if (!reset_n)
        count <= 0;
      else
        if (en)
          count <= count + 1;
   end
endmodule // count4