Pretty much only testbenches are "software" in VHDL, otherwise you are writing hardware descriptions. So if you need something that teaches you how to use VHDL as software then something along the lines of a book on testbenching with VHDL might be more your cup of tea, e.g. "Writing Testbenches: Functional Verification of HDL Models, by Janick Bergeron is one such book. I have no idea if it is any good, but the reviews on Amazon seem to indicate it's alright.
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BTW running simulations isn't an easy introduction for a software type for learning VHDL, it's specifically for verifying your hardware descriptions functionality.