blowfish
Member level 4
Hai,
I am working on digital delay locked loop using verilog HDL but , i am not able to get any reference paper in which the entire simulation is done using verilog HDL. So that i can fuse it in an FPGA kit or performe the ASIC design .
Some papers they dont tell in which tool they simualted the design . As some circuits are given as digital circuits but some modules are given as analog or in circuit level.
please send any paper or ideas which can help me.
I am working on digital delay locked loop using verilog HDL but , i am not able to get any reference paper in which the entire simulation is done using verilog HDL. So that i can fuse it in an FPGA kit or performe the ASIC design .
Some papers they dont tell in which tool they simualted the design . As some circuits are given as digital circuits but some modules are given as analog or in circuit level.
please send any paper or ideas which can help me.