I am working on digital delay locked loop using verilog HDL but , i am not able to get any reference paper in which the entire simulation is done using verilog HDL. So that i can fuse it in an FPGA kit or performe the ASIC design .
Some papers they dont tell in which tool they simualted the design . As some circuits are given as digital circuits but some modules are given as analog or in circuit level.
please send any paper or ideas which can help me.
Re: could anyone share ideas on digital DLL using verilog H
Hi,
I dont get much information on the DLL design and its concepts on the net ,as DLLs are new the industry . So please take some time and post your knowledge about DLLs, which will help many of us ...
Thanks in advance.