I dont remember where i got this page from, but i had saved it as a doc file. (I take no credit for this info....i found it on a brilliant page which i have forgotten the link to ! )
Take a look at the doc file....i am currently doing a project on it....writing a verilog code for it.....so if u need more help .....here i am
the rom size used in cordic is quite small, let's say, small enough. But as cordic consumes clocks in computing result with precision., you may clearly find out whether a certain precision cordic algo meets your data throughput rate.
Cordic algorithm converges quite fast and is quite accurate after around 15 iterations. What you can do to solve the rom problem if to make the rom values a combinational circuit (which would be quite small assuming you are using a large logic device).