Correlation between signoff & implementation flow

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fail1

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Hi,

Say, I have done Place & route for my design using Cadence/Magma & doing signoff checks now.
What are all the things to look for if you see a correlation issue between implementation & signoff tools?

Is there any doc/white paper which explains all the key points to debug the issue?

Thx
Kumar
 

About the signoff check items: timing, clock_transition, data_transition, max_cap, glitch, doubleswithching, min_pulse_width, and so on.
In the implemention flow, you need to preserve some margin for the signoff tools.
 

When you used a new technology, or for each new circuit, you must done one time a correlation between the spef generated by the PR tool and the spef generated by the signoff tool. With this information you can ajust the R & C factor on the PR tool to be more accurate.

After this you need to check the same path on both tool, and understand the difference, you will see, the cell/net delay, cap...

Sometimes, the SDC is not correctly understand between both tools...

good luck
 

Before routing, we need to correlate the delay calculator of APR(socfe) with signoff tool(primetime).

After routing, we need to correlate the RC extraction engine of APR(socfe) with signoff extraction tool(starRCXT)
 
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