I noticed for some SD ADC designs, ppl use CDS to decrease integrator leakage and flicker noise. For those of designs that circuit noises are the dominant noise sources (i.e. quantization noise is not so obvious), how can I model flicker noise and white noise properly if CDS is employed? thanks.
What if the input parasitic capacitance of the opamp is considerably large?
Have you ever done any simulation to explore the noise spectrum w/ CDS in transistor level? I want to plug the noise spectrum in the SIMULINK SD Toolbox, kind of lost that how I can properly simulate.
BTW, anybody know how to realize z^(-1/2) in simulink?
large input parasitic capacitance of opamp will increase the settling time constent of integrator, so increase the power dissipation
i hear of CDS can be simulated by spectreRF, but i don't try it
in fact, when i model the noise of opamp in SD toolbox, i consider the thermal noise only, maybe this isn't very accuracy
There are several papers claim the input parasitic capacitors can seriously degrade the low-frequency noise performance in CDS. If you are interested in, I can forward those papers to you.
I'm dealing with a high precision Mash now and circuit noise is the limit of my design. That's why I need to model everything properly. I found a way to do the Z^(-1/2) in matlab: using rate transition.
i don't consider the effect of input parasitic capacitance, it's my fault. it must be helpful if you send the related papers to me, thank you very much. my address is ginger1977@163.com
i'm designing a high-resolution mash too maybe chopper is feasible too which reduce the 1/f noise, i'm trying it