Corner Simulations in Spectre

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Sezi

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I have a PLL working very well with tt (typical) transistors but not with ss (slow pmos slow nmos) transistors. Well what would you suggest? widen the transistors for speed up? I don't have an idea what to do when ss simulation fails..?
 

hmm i haven't.. actually i think that's the problem cause it locks to the frequency of interest with a much different control voltage. but still the pll locks.. the problem is, it's not a simple pll but a clock recovery circuit. so the retimed data is not equivalent to incoming data.. i shall simulate the vco with corners.. thank you
 

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