Coregen from xilinx ip core it doesn't show the code

[amithsanu]

everyone tells use coregen from xilinx.. but as it is an ip core it doesnt shw the code...just the i/p o/p parameters and function declarations... If i want to make use of those in my code..wt is the procedure exctly???for example consider calculation of sine and cosine values and explain me..???

 

[philoman]

coregen...ip cores????

Well, it depends on your design flow.
For example, you can use VHO as a instantiation template file in a vhdl desing flow. After instantiating a core in your ISE Project Navigator project, you may also want to add the core (XCO file) to you project, which will lit up core's icon in hierarchy pane. Otherwise, a quesion mark indicates the source file missed.

 

[hassantalal785]

Re: coregen...ip cores????

Well after defining the parameters for your IP core using LOGICORE GUI of Xilinx . a folder with certain files would be made in the directory as specified by u in the start of LOGICORE GUI . In that folder there would be .v file .. open it using notepad++ or with any other thing there .. there in the start certain inputs and outputs would be written in brackets and it would be followed by computer generated code which is of no use to you .. so just INSTANTIATE the inputs and outputs in your Top level level moodule ... i hope u understand .....???