edif to verilog xilinx
hi andrepandi, you can change the output netlist type in ISE, by changing the properties of "PAR" stage.
in ISE, there is one step "PAR" while building the project.by right clicking the PAR tab, we can get the properties. there is one option " output netlist type" with the options edif,verilog,vhdl. by default edif will be there.
Added after 38 seconds:
hi andrepandi, you can change the output netlist type in ISE, by changing the properties of "PAR" stage.
in ISE, there is one step "PAR" while building the project.by right clicking the PAR tab, we can get the properties. there is one option " output netlist type" with the options edif,verilog,vhdl. by default edif will be there.