Converting Verilog Description to EDIF netlist

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viswanadh

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Hello,

Anybody knows if it's possible to convert a Verilog module into an EDIF netlist file? Can EDIF file represent a verilog module completely? Please help me. If my question doesn't make any sense, sorry :|

Thanks
 

my guess is, if synthesized using DC or any other tool, its possible to convert it to EDIF. to my knowledge, EDIF does represent verilog module completely, albeit with the technology library's cells, ofcourse.
 

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    viswanadh

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edif is an IEEE standard to represent HDL module. Any verilog module can be equivalently written in edif. U can use ur sysnthesis tool to write out edif netlist also.
 

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    viswanadh

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Thanks for the replies. I've found a way to convert the verilog modules using "iVerilog" It uses LPM s (libraries) in the EDIF files.
 

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