Hi,
Synopsys has a tool design compiler. Following is a method to create gate level equivalent for There GTECH library.
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To create a netlist with gates that are technology independent, you should use
a generic library, such as the generic technology (GTECH) library that Design
Compiler uses. Then to avoid DesignWare components in the netlist, compile the
design with the GTECH library as the target library.
The following tool command language (Tcl) script will give you the result you
want: a netlist made out of generic library cells.
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set synthetic_library "dw_foundation.sldb"
set target_library " ..../U-2003.06-1/libraries/syn/gtech.db"; # Change here to your installation path
set link_library "* $target_library $synthetic_library"
read_verilog { all verilog files of the design }
compile
change_names -rule verilog
write -out design_name.gtech -hier -format verilog
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If you are using any other synthesizer ....find procedure equivalent to the gievn above.
bye,
Ram