Re: matlab to vhdl
ragabs,
I have personally tried running a design in VHDL using ModalSim v5.x, and testing my design on Matlab on (1) a image processing project and (2) an audio processing project in the past.
I don't think there is yet a conversion tool from Matlab to VHDL that is readily available in the market. But I think there could be some in-house tools in some companies that does this.
I have heard of a way from old friends in the ASIC industry. What they did was actually modifying the C lang statements in your .c file and implement them in the Process statement in .vhd to maintain the sequential nature, not unless you want some concurrent statements which in fact doesn't happen in C.
Additional viewpoint
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I am seeing biased judgement against VHDL. That's not a very ethical to make, especially in engineering practices.
First and foremost, VHDL and Verilog works with some abstraction levels in common, although VHDL targets more of the system level abstraction and Verilog more to the circuit level abstraction.
I need to highlight the fact that both VHDL and Verilog originated from the USA, although USA seems to prefer imparting Verilog whereas Europe prefers VHDL.
Take note that the IEEE Circuits and Systems Society has its mainstream beginning to change side from Verilog to VHDL in the recent years being the fact Verilog is very much detached from high-level support because system architecture is shifting towards CONVERGING high and low.
I have also seen IEEE members, who are hardcore Verilog, mainly from the USA, beginning to soften in the past years when VHDL is seeing importance from the developments made in Europe and Asia Far East, especially when it comes to development of EDA CAD tools, modelling tools, synthesis tools, high-level language capatibility etc. VHDL is perhaps the only HDL we use or know that can bridge the gap between low level circuit and high level languages.
So I guess it is time not to bring in personal judgement against VHDL, despite this is a long American tradition wherever I go. I always hear discriminating opinions when my friends and I go to conferences in the States. I know the Americans seem to dislike VHDL very much.
Well... Both VHDL and Verilog are languages to help us solve problems in engineering, not something for us to argue over. That's my opinion to uphold ethical engineering practices.
One thing to note. It is an established fact that VHDL is harder to master than Verilog, based on statistics made in engineering education. Many academic professors also told me that students learn Verilog better than VHDL. So don't complain about VHDL when you cannot master it. If so many engineers can handle VHDL, why can't you? You just need to spend more time to learn it well. Not blaming it.