Converter Bandwidth vs Output Filter Resonant Frequency

[with2ls]

Hi Everyone,

I have what I think is a general question that I can't seem to get a clear answer on:
Strictly considering Converter Bandwidth and Output Filter Resonant Frequency in a voltage loop, should the converter compensator be designed to ensure the Converter Bandwidth is greater than the Output Filter Resonant Frequency?

I ask because I am having issues tuning the outer voltage loop on a voltage source inverter. Currently the Converter Bandwidth is less than the Output Filter Resonant Frequency, and the Resonant gain bump is killing the gain margin.

Any input is appreciated. Thanks!

 

[cupoftea]

Good point, i thought VSI's were pretty much open loop.....you just give sinusoidal PWM and you get a sine output with a peak voltage just below the DC input voltage. As such, i am not sure what feedback loop you speak of.?
As you know, the peak of the outputted sine can indeed be changed, but doing so need never be done quickly, just change the sine PWM dutys. Though more likely you would just reduce the VDC input, and keep the sine PWM the same.

 

[with2ls]

Thanks for the reply, the design is similar to this TI reference design:

https://www.ti.com/lit/pdf/tiduay6

The control method contains an inner current loop and an outer voltage loop, as well as feedforward. I can get it to run fine with purely resistive loads, but non-linear loads (such as a simple rectifier and resistor) cause distortion.

 

[with2ls]

I'm sorry, I should have stated the control loop is described in Section 2.2.3 Control Scheme (page 11), in the link in the previous post.