This error is because you have more than one package that declares an unsigned type. You didnt post the code, but I assume you have included std_logic_arith and numeric_std. You should delete std_logic_arith as it is a non-standard VHDL library.
You have another problem: you're trying to convert std_logic to unsigned. Thats impossible, because std_logic is an enumerated type, and unsigned is an array of std_logic. They are not related types.
You will need to make an array out of your single std_logic bits to make them unsigned. There is a nice little hack for this - simply append the bit to a null array. You will also need to qualify the resulting array as unsigned so it doesnt get confused between unsigned and signed:
Code VHDL - [expand] |
1
| a <= std_logic_vector( unsigned'(""&h) + unsigned(""&f3) ....... etc |
Of course, it would have been much easier if a and the other signals were all unsigned in the first place.