[SOLVED] Conversion of std_logic to integer in VHDL

tahirsengine · Sep 19, 2018

Hi,
I know this topic is being discussed earlier, but I think my issue is little different.
Here is my test code:

Code:

-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity micro_test_file is
 Port (clk_in: in std_logic;
       the_input: in std_logic_vector(0 to 3); 
       the_output: out std_logic_vector(0 to 7)
       );
end micro_test_file;

architecture Behavioral of micro_test_file is

type dummy_array is array (0 to 2) of std_logic_vector (0 to 7);
signal ins_dummy: dummy_array := (8x"A",8x"B",8x"C" ); 
begin
process(clk_in)
begin
the_output(0) <= ins_dummy(to_integer(unsigned(the_input(0 to 1)))); -- here it is complaining "indexed name is not std_ulogic"
the_output(1) <= ins_dummy(the_input(0 to 1));
the_output(2) <= ins_dummy(the_input(0 to 1));
the_output(3) <= ins_dummy(the_input(0 to 1));
end process;
end Behavioral;
-----------------------------------------------------------------------------------------

Actually in the main circuit, I am receiving input from outside my module as 32-bits. So I want to use chunk of it to address some internally declared(and initialized) array.

What may be work around?
Please note that I am still in learning phase of VHDL so please be gentle :-D

Cheers
tahir

- - - Updated - - -

the_output(0) was the problem. Removed (0). And it worked, as previously I was trying to assign a whole 8 bit value to a single bit.

Thanks guys.

TrickyDicky · Sep 19, 2018

There are several problems with this code
1. You have clk_in in the sensitivity list, but you have not created a synchronous process, so no registers will be infered. You need to do an edge detection on the clk to do that:

Code VHDL - [expand]
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process(clk)
begin
  if rising_edge(clk) then
    -- synchronous code goes here
  end if;
end process;

While it may look like synchronous code in a similation it will change the outputs on both clock edges and it will only infer a wire when you try and synthesise it.

2. No of "the_output" assigns will work, as the indexing into ins_dummy needs to be an integer, and all of the indexes are std_logic_vectors.

3. You have made ins_dummy a signal, but it is never assigned. It would be better as a constant (to infer a rom).

tahirsengine · Sep 19, 2018

TrickyDicky said:
There are several problems with this code
1. You have clk_in in the sensitivity list, but you have not created a synchronous process, so no registers will be infered. You need to do an edge detection on the clk to do that:

Code VHDL - [expand]
1 2 3 4 5 6
process(clk) begin if rising_edge(clk) then -- synchronous code goes here end if; end process;

While it may look like synchronous code in a similation it will change the outputs on both clock edges and it will only infer a wire when you try and synthesise it.

2. No of "the_output" assigns will work, as the indexing into ins_dummy needs to be an integer, and all of the indexes are std_logic_vectors.

3. You have made ins_dummy a signal, but it is never assigned. It would be better as a constant (to infer a rom).

Here is a better version of the same code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity micro_test_file is
 Port (clk_in: in std_logic;
       the_input: in std_logic_vector(0 to 3); 
       the_output: out std_logic_vector(0 to 7);
       the_out_1 : out integer
        );
end micro_test_file;
 
architecture Behavioral of micro_test_file is
type dummy_array is array (0 to 2) of std_logic_vector (0 to 7);
signal ins_dummy: dummy_array := (0 => 8x"F", 1 => 8x"B", 2 => 8x"C"); 
signal the_output_r: std_logic_vector(0 to 7) := 8x"0";
 
begin
process(clk_in)
begin
if rising_edge(clk_in) then 
the_output_r <= ins_dummy(to_integer(unsigned(the_input(0 to 1))));
the_out_1    <= to_integer(unsigned(the_input(0 to 1)));
end if;
end process;
the_output <= the_output_r;
 
end Behavioral;

Now in the test bench when I try to access the values of ins_dummy elements, it just gives me the first value. Here is a part of test bench:

Code VHDL - [expand]
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main_process: process
begin
the_input <= 4x"2"; 
wait until  rising_edge(clk_in);
the_input <= 4x"1"; 
wait until  rising_edge(clk_in);
the_input <= 4x"2"; 
wait until  rising_edge(clk_in);
the_input <= 4x"0";
wait until  rising_edge(clk_in);
end process main_process;
 
end Behavioral;

Actually what I want to do is as follows:
I will read values from an input(the_input(1 to 0)) hex values. Then I will give part of that into an array(dummy_array) and read that array values to output(the_output).

Any solution suggested?

[SOLVED] Conversion of std_logic to integer in VHDL

tahirsengine

Member level 3

TrickyDicky

Advanced Member level 7

tahirsengine

tahirsengine

Member level 3

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Code VHDL - [expand]
1 2 3 4 5 6	process(clk) begin if rising_edge(clk) then -- synchronous code goes here end if; end process;

[SOLVED] Conversion of std_logic to integer in VHDL

tahirsengine

Member level 3

TrickyDicky

Advanced Member level 7

tahirsengine

Member level 3

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