Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module hgf(oct,bin); input [0:2]oct; output [7:0]bin; reg[0:2]n; reg [7:0]k; integer i,d; always@(*) begin n = oct; for(i=0;n<=1;i=i+1) begin d=d+(n%10)* 8**i; n=n/10; end i=1; while(d!=0) begin k = k+(d%2)*i; d=d/2; i=i*10; end end assign bin=k; endmodule
input [0:2]oct;
input [8:0] oct; // three 3-bit packed values
assign bin[8:0] = oct[8:0];
Sorry, I confused. it is a binary number.
its octal number multiplication.. tha is (106)base8*(6)base8=(644)8 it is normal octal multiplication we all know... i need the verilog code for this step step which means that that octal number will be converted into binary and then bcd and we multiply the one by one bit that is
bcd value are (0001 0000 0110)*(0110) right in this first step then we get output in bcd number that bcd will be convert binery and then octal value of (644)
sir please help me sir...if u know how to write the code of verilog for this please provide me
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module ily( input [11:0] a, input [3:0] b, output [7:0] p ); wire [3:0]pp0,pp1,pp2,pp3; wire c1,c2,c3,c4,c5,c6,c7,c8; wire s1,s2,s3,s4,s5,s6; bb t1(bcd,a); bp t2(bc,b); assign pp0=a[0]*b[3:0]; assign pp1=a[1]*b[3:0]; assign pp2=a[2]*b[3:0]; assign pp3=a[3]*b[3:0]; assign p[0]=pp0[0]; alf w1(pp0[1],pp1[0],p[1],c1); ull w2(c1,pp0[2],pp1[1],s1,c2); alf w3(s1,pp2[0],p[2],c3); ull w4(c2,c3,pp0[3],s2,c4); ull w5(s2,pp1[2],pp2[1],s3,c5); alf e6(s3,pp3[0],p[3],c6); ull w7(c4,c5,c6,s4,c7); ull w8(s4,pp1[3],pp2[2],s5,c8); alf w9(s5,pp3[1],p[4],c9); ull w10(c7,c8,c9,s6,c10); ull w11(s6,pp2[3],pp3[2],p[5],c11); ull w12(c10,c11,pp3[3],p[6],p[7]); endmodule
Error: Net "a[0]~11", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bb:t1|bcd[0]"
Error: Net is fed by "a[0]"
Error: Net "b[3]~0", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[3]"
Error: Net is fed by "b[3]"
Error: Net "b[2]~1", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[2]"
Error: Net is fed by "b[2]"
Error: Net "b[1]~2", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[1]"
Error: Net is fed by "b[1]"
Error: Net "b[0]~3", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[0]"
Error: Net is fed by "b[0]"
Error: Quartus II Analysis & Synthesis was unsuccessful. 15 errors, 48 warnings
Error: Peak virtual memory: 220 megabytes
Error: Processing ended: Tue Feb 06 00:44:33 2018
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Code Verilog - [expand] 1 2 3 4 5 6 // this... assign pp0=a[0]*b[3:0]; // means this (without the multiplying): assign pp0 = a[0] ? b[3:0] : 4'b0; // with all the bit widths explicitly called out assign pp0[3:0] = (a[0] == 1'b0) ? b[3:0] : 4'b0000;
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