ghostridergr
Member level 1
Can anyone help me in that:
where it is:
The compiler complains "No feasible entries for conv_signed". But as i see in std_logic_arith it can take as argument an std_ulogic. What i 've done wrong?
Code:
read_inp: for k in 0 to N-1 loop
a(k)<=to_stdulogic(a_var(k));
end loop;
wait for 1 ms;
inp1(1,1)<=conv_signed(a,N-1);
where it is:
Code:
signal a,b: std_logic_vector(N-1 downto 0):= (others=>'0');
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