read_inp: for k in 0 to N-1 loop
a(k)<=to_stdulogic(a_var(k));
end loop;
wait for 1 ms;
inp1(1,1)<=conv_signed(a,N-1);
where it is:
Code:
signal a,b: std_logic_vector(N-1 downto 0):= (others=>'0');
The compiler complains "No feasible entries for conv_signed". But as i see in std_logic_arith it can take as argument an std_ulogic. What i 've done wrong?
yes but if i use numeric_std which the function to_signed doesn't as an argument std_logic_vector. Thats why i used ulogic, so as to do the conversion with conv_signed. What changes do you propose?
These are my imports:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;