actually, VHDL also allows "unconstrained" ports for components in the same way it is allowed for functions. eg, a port could be declared as "in std_logic_vector;". There are some practical implications:
1.) 'length-1 downto 0, 'high downto 0, and really even "downto" may not work as expected. this is because the unconstrained port takes the dimension of the connected signal. eg connecting x(7 downto 4) to a 4 bit _unconstrained_ port means that the port is 7 downto 4, not 3 downto 0. trying to index bit 0 within the entity no longer works, while 'low still does.
2.) outputs must be connected to non-opens. outputs also must be properly sized even if not used. The latter is because the 'length of an output might be needed for the proper operation of the instance. This is an annoying requirement.
3.) inputs must be connected to the correct size signal, even when not used. "0000" defaults to 0 to 3, which again causes issues when the direction is assumed to be downto.
4.) there is no immediate context of the size of ports. eg, an unconstrained ram might be expected to have read/write data widths equal, and read/write addresses equal, and byte write enables equal to data width divided by 8. with unconstrained vectors, this might not be obvious -- the user might assumes the width conversions are done because there is nothing that prevents the connections of a 32b read port and 16b write port. when generics are used, the meaning is clear.
5.) size checking isn't done automatically. thus an output, y, defined in terms of an input x as x'length/8 can have issues when the user connects y to a larger vector. in such a case, the upper bits are not driven -- a warning.
Overall, unconstrained vectors are mixed. They can be used to make some modules easier to use, but the above nuances can allow for subtle bugs to creep into the design. eg, when bits N-1 downto 1 of an N-bit vector are used. If the user connects an N downto 1 vector, which has the same 'length as the expected N-1 downto 0 vector, the component will still synthesize. The results will not be as expected, as the lsb is now used.
as a result, entity that make use of unconstrained vectors often use a signal x_normal such that x_normal(N-1 downto 0) <= x; which maps "x" into the expected form. likewise, assert statements should be added, and size checking should be done.