casey480
Junior Member level 1
i have a generated clock 'i_clk' which is a divide by two created from a flip flop clocked by 'user_clock'
thus, i have the following constraint:
i_clk is also an output of the module. my question is, how do I constrain that output?
i currently have
however, I get min timing violations on that port. Am I doing this correctly?
thus, i have the following constraint:
Code:
create_generated_clock -source [get_pins user/user_clk_mux/O] [get_pins user/i_clk_reg/Q] -name I_CLK -divide_by 2i_clk is also an output of the module. my question is, how do I constrain that output?
i currently have
Code:
set_output_delay -max 16 -clock I_CLK {i_clk}however, I get min timing violations on that port. Am I doing this correctly?