Constraining a combinational path through a black box

[sherry151]

Hi,

I have a combinational path that goes through a black box RAM. I am unable to find an accurate way to constrain this path. I do not have the .lib file for the RAM. I know the read latency of the RAM though. Conceptually this should be very simple as I just need to tell the tool that even though the connection from the address input to the address output of the RAM is not visible, there is in fact a connection and the delay for that connection is 'X ps' . Then the tool can easily optimize the logic on both sides of the RAM easily.
A second option, which I know how to do, would be to split up the clock cycle into, say, half on each side and use max_delay -to and max_delay -from constraints on the input and output side of the RAM respectively also taking into account the read latency.

Tool Used: Design Compiler


Thanks!

 

[OhaAmo]

Sounds odd that you use a memory that you don't have the .lib file of it provided.
You should use the vendor's .lib file of the RAM, or to create one by yourself.
As you said, you can use set input/output delay of the memory pins, it might work.