Sounds like a misunderstanding of DDS principle. You can get pretty low jitter after the DDS output filter with a carrier fulfilling the Nyquist criterion, achieving low jitter is much more a problem of sufficient DAC resolution. Consider that DDS is often used to generate a continuously frequency variable digital clock, without much carrier frequency overhead, a way of trading magnitude resolution against phase resolution.You have to add ~8bit on top of high frequency range to avoid phase jitter, which brings 24 bits you have calculated to 32 bits.
I meant DPLL, a fully digital PLL solution.I know what is PLL, but what is DLL stands for?
with a NCO the stepsize is constant.What is "logarithmic solution"?
Hi,
Correct me if I´m wrong.
To me it seems you rather need a constant "percentage" step size than a fixed frequency step size.
Klaus
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