Connection of body of nwell resistor in layout in cadence
For layout of nwell resistor in cadence, how should the substrate be connectted? what kind of contact should I use? Or, what is the material that forms substrate of nwell resistor? The process I am using is charted 0.18um process. Thanks a lot.
Re: Connection of body of nwell resistor in layout in cadenc
Peter_Dn said:
Connection of body of nwell resistor in layout in cadence
For layout of nwell resistor in cadence, how should the substrate be connectted? what kind of contact should I use? Or, what is the material that forms substrate of nwell resistor? The process I am using is charted 0.18um process. Thanks a lot.
Since you are using n-well resistor, it is laid-out directly to psub/pwell. Ptap should be put around the resistor inside the psub/pwell and should also be connected to vss. Same rule as other n-type devices is applied.
Re: Connection of body of nwell resistor in layout in cadenc
Hi!
I'm trying to do an nwell resistor in umc 0.18um.
Could someone tell me how to do it? I think I have to use a Twell but I'm not sure, and if I have to, I don't know exactly which layers do i have to use, and how to biasing them
Re: Connection of body of nwell resistor in layout in cadenc
As protonixs point out in a P-epi or P-substrate process the body is PEPI or PSUB so can not connected to anything. Only if you using a parasitic substrate resistance extraction there could be local connection to sub_layoutcellinstance. But this is typical handled in advanced design enviroments by the tools. So as a designer you do not have acces to the body terminal.
For a Triple-Well process there could be a PWELL-resistor in a NWELL. In this case the body is the NWELL and should/must be connected to a higher potential than any resistor terminal.