module A (inout_bus_a, en_a);
inout [7:0] inout_bus_a;
input en_a;
reg [7:0] inout_bus_a_reg;
assign inout_bus_a = (en_a) ? 'bz : inout_bus_a_reg;
always () begin
read_from_bus_data = inout_bus_a;
........
........
inout_bus_a_reg = write_to_bus_data;
........
........
end
endmodule
module B (inout_bus_b, en_b);
inout [7:0] inout_bus_b;
input en_b;
reg [7:0] inout_bus_b_reg;
assign inout_bus_b = (en_b) ? inout_bus_b_reg : 'bz;
always () begin
read_from_bus_data = inout_bus_b;
........
........
inout_bus_b_reg = write_to_bus_data;
........
........
end
endmodule
module top;
wire [7:0] inout_bus;
reg en_b; // this needs to be driven by top
A (inout_bus, en_b);
B (inout_bus, en_b);
endmodule