lostinxlation
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Could someone tell me how to connect unpack arrays in system verilog in the following example ?
Now I want to connect primary input, in[0], to in[0] and in[1] of sub, and connect primary input, in[1], to in[2] and in[3] of sub.
I want to connect them like(I know it is not legal, but just gives you some idea on what I want to do),
how can I achieve this without assigning in[1:0] to other variables ?
many thanks,
Code:
module sub (
input [31:0] in [0:3];
....
);
endmodule
module top (
input [31:0] in [0:1];
....
);
sub sub (.in(????????));
endmodule
Now I want to connect primary input, in[0], to in[0] and in[1] of sub, and connect primary input, in[1], to in[2] and in[3] of sub.
I want to connect them like(I know it is not legal, but just gives you some idea on what I want to do),
Code:
sub sub(.in({2{in[1]}}, {2{in[0]}});
how can I achieve this without assigning in[1:0] to other variables ?
many thanks,
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