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| library ieee;
use ieee.std_logic_1164.all;
entity vj_block is
port (
-- inputs:
MAX_VER : IN STD_LOGIC_VECTOR(7 downto 0);
board_ID : IN STD_LOGIC_VECTOR(15 downto 0);
pushbutton : IN STD_LOGIC_VECTOR(1 downto 0);
cap_sense : INOUT STD_LOGIC;
-- outputs:
led_ctrl : OUT STD_LOGIC_VECTOR(1 downto 0)
);
end vj_block;
architecture rtl of vj_block is
component vj_inf
PORT(
ir_out : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tdo : IN STD_LOGIC ;
ir_in : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
tck : OUT STD_LOGIC ;
tdi : OUT STD_LOGIC ;
virtual_state_cdr : OUT STD_LOGIC ;
virtual_state_cir : OUT STD_LOGIC ;
virtual_state_e1dr : OUT STD_LOGIC ;
virtual_state_e2dr : OUT STD_LOGIC ;
virtual_state_pdr : OUT STD_LOGIC ;
virtual_state_sdr : OUT STD_LOGIC ;
virtual_state_udr : OUT STD_LOGIC ;
virtual_state_uir : OUT STD_LOGIC
);
END component;
component data_enc
port (
clk : IN STD_LOGIC;
cdr_in : IN STD_LOGIC;
ir_in : IN STD_LOGIC_VECTOR(2 downto 0);
vj_add : IN STD_LOGIC_VECTOR(3 downto 0);
reg : IN STD_LOGIC_VECTOR(15 downto 0);
board_ID : IN STD_LOGIC_VECTOR(15 downto 0);
pushbutton : IN STD_LOGIC_VECTOR(15 downto 0);
disp_out : OUT STD_LOGIC
);
end component;
component address_dec
port (
clk : IN STD_LOGIC;
data_in : IN STD_LOGIC;
ir_in : IN STD_LOGIC_VECTOR(2 downto 0);
sdr_in : IN STD_LOGIC;
e1dr_in : IN std_logic;
address_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
led_ctrl : OUT STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component capacitive_pbs
port(
pb : INOUT STD_LOGIC;
grn_led : OUT STD_LOGIC := '0'
);
end component;
signal tck, cdr, tdo, tdi, sdr, e1dr, grn_led : std_logic;
signal ir_in : std_logic_vector(2 downto 0);
signal vj_add : std_logic_vector(3 downto 0);
signal reg : std_logic_vector(15 downto 0);
signal data : std_logic_vector(15 downto 0);
begin
u1: data_enc PORT MAP(tck, cdr, ir_in, vj_add, reg, board_ID, data, tdo);
u2: address_dec PORT MAP(tck, tdi, ir_in, sdr, e1dr, vj_add, led_ctrl);
u3: capacitive_pbs PORT MAP(cap_sense, grn_led);
vj_inf_inst : vj_inf PORT MAP (
ir_out => ir_in,
tdo => tdo,
ir_in => ir_in,
tck => tck,
tdi => tdi,
virtual_state_cdr => cdr,
virtual_state_e1dr => e1dr,
virtual_state_sdr => sdr
);
data<= "0000000000000" & pushbutton & grn_led;
reg <= '0' & "00000" & '0' & '0' & MAX_VER;
end rtl; |