Connecting a SAR ADC system in verilogA

[nijMcnij]

+veriloga +switch +case

hello all,

i am trying to simulate the system behaviour of a charge redisrtibution SAR ADC, i have created the modules for the comparator, capacitors, switches and control logic in verilogA, and then i created the symbols as pointed out in the comments, what remains now is to connect the entire system in a single schematic and then run the simulation....that is what i didn't figure out yet.

1-how do add a sin wave source with a specific frequency and amplitude?...i know of this function vsource(), but can i add vsource or vsin from the library manager?

2-how do i set up the ac simulation (ac, dc,transient, or what have u)...can i use the analog environment and just click choose analysis--->dc ?

3-how do i plot the outputs and see waveforms?

many thanks

 

[safwatonline]

shift register veriloga model

hello,
after creating the blocks just treat them as any block that is already available, use the schematic entry then analog enviroment , choose the waves to plot then choose the type of simulation ac trans.,etc.
just as any other simulation w/o veriloga , note i dont know if this will work if u have some blocks in verilog "i think in this case sprectre will need to simulate mixed signals ,i think there is a specific simulator for that ,but not sure"
anyway it works with me when using verilogA.
hope this help,
regards.
a.safwat

 

[nijMcnij]

veriloga buffer

thank you safwatonline for your help,

my models both analog (comparator, capacitors, switches...) and digital parts (clk generator, shift register).

so you are saying that i should only add all the blocks to the schematic and then start analog environment and choose the analysis type from the "Analyses" list.

but what about the signal sources....for my particular case i want to test the ADC with a sin wave....can i use the vsin from the analoglib library ?

many thanks

Added after 38 minutes:

i tried to connect a simple buffer (veriloga module) with a "Vdc" source from analogLib and a resistor at the buffer output ,and i choose the simulation type to be "dc"....

i keep getting netlister errors.....can't decend to any of the views defined

any idea what am i doing wrong here?

thanks

 

[yaxazaa]

Re: verilogA question

If you top level SAR ADC schematic includes verilog, then you need both spectre and verilog license to run in cadence enviorment.

 

[nijMcnij]

Re: verilogA question

but as i told u before, i just tried a simple buffer module (no digital parts at all).....i connected the input port to a "Vdc" and the output to a resistor ....and i got errors

 

[Hughes]

Re: verilogA question

i tried to connect a simple buffer (veriloga module) with a "Vdc" source from analogLib and a resistor at the buffer output ,and i choose the simulation type to be "dc"....

i keep getting netlister errors.....can't decend to any of the views defined

any idea what am i doing wrong here?

Did you check the switch view list file in the setup environment form? It should contain the veriloga view name (veriloga by default). If not, please add it.