I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional Verilog module? Can I both use modport and instance the module? Or is there any walk around method? Thanks!
Hi Yes u need to declare an interface and modports to indicate direction. I am uploading one ppt. Kindly go through that. I think that will be beneficial for you.