I have done (or ordered it done) on occasion. A small chip capacitor can
be skip-bonded (wedge) or multi-point bonded (gold ball) if you want the
capacitor to connect to more than one place. Depending on circuit topology
the package cavity floor can also be a useful (or unavoidable) connection.
If you need an isolated cap you may want a bare-floor ceramic package.
Of course none of this is very useful for a mass production plastic package.
But this is not that (yet).
You might even find specialty capacitors with both terminals on the top side
if you look; surface mount chip caps might be mounted bottom-up and an
un-solder-bumped pad might stick the landing.
One Question,
What is the advantage to doing this at all over just doing a simulation with different capacitor values?
The external capacitor will come with its own non-idealities, ESR, and all. Also, there would be so much extra parasitics which would get added to the nodes which are now connected to the pads.
Also, what is the value of the capacitor that you want to add here?
Sooner or later you need to get real. If that's what they're paying
you for. Of course you can learn wrong things from breadboards
too. Which is what this is, only minimal. Physical mockups at
macro scale have their own parasitics as will the bond wire.
Get your wire data for ohms and figure 1nH/mm and hope there
is no coupling to model. If this is not GHz RF then you should be
fine.
If you're cutting trail then simulation is not to be relied upon,
only used as a direction finder. Primitive methods for primitive
conditions.