connect all the clock gating test pins to a port in RTL compiler

zhangljz · Oct 14, 2015

Hi,

I am using RTL compiler for synthsise, and I want to implement clock gating. I don't have ICG cell, so I wrote a module as the clock-gating module, which has "ck, D,Q,enable, test", where test is the clock gating control signal.

Code Verilog - [expand]
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module ICG_posedge (
input ck_in, enable ,test,
output ck_out
);
 
reg en1;
wire tm_out, ck_inb;
 
assign tm_out = enable | test;
assign ck_inb = ~ck_in;
 
always @(ck_inb, tm_out)
  if(ck_inb)
     en1 = tm_out;
 
assign ck_out = ck_in & en1;
 
endmodule;

The question is that I want to connect pin 'test ' of all the ICG instances together to a port 'CG_test'. How can I do this in RTL compiler?

Thank you

artmalik · Oct 14, 2015

it is not a good idea to implement a clock gater cell because of timing issues with gates put in the clock gate. as far as I have seen...most library vendors will provide a set of clock gaters(I have yet to see a library with clock gaters).
Clock gaters are bit complicated and specially handled by tools because they go into the clock tree. you should ask your vendor to provide the clock gater in the library

connect all the clock gating test pins to a port in RTL compiler

zhangljz

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artmalik

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connect all the clock gating test pins to a port in RTL compiler

zhangljz

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