AdvaRes
Advanced Member level 4
20 log
Hi all,
I have confusions regarding VCO phase noise. I was reading the following document when the confusions arises.
https://www.analog.com/library/analogDialogue/archives/33-05/phase_locked/PLLs_2.pdf
The autors says that
If we want to estimate the contribution of the
PLL device (noise due to phase detector, R&N dividers and the
phase detector gain constant), the result must be divided by N²
(or 20 ´ logN be subtracted from the above result). This gives a
phase-noise floor of [–85.86 – 20 ´ log(9400)] = –165.3 dBc/Hz.
How is that ? How does 20log(N) represent the noise due to the other components of the PLL ?
Second, I expected addition instead substraction. Coz at the best case the PLL phase noise is equal to the VCO phase noise if we dont consider the other phase noise ?
Could someone explain ?
Hi all,
I have confusions regarding VCO phase noise. I was reading the following document when the confusions arises.
https://www.analog.com/library/analogDialogue/archives/33-05/phase_locked/PLLs_2.pdf
The autors says that
If we want to estimate the contribution of the
PLL device (noise due to phase detector, R&N dividers and the
phase detector gain constant), the result must be divided by N²
(or 20 ´ logN be subtracted from the above result). This gives a
phase-noise floor of [–85.86 – 20 ´ log(9400)] = –165.3 dBc/Hz.
How is that ? How does 20log(N) represent the noise due to the other components of the PLL ?
Second, I expected addition instead substraction. Coz at the best case the PLL phase noise is equal to the VCO phase noise if we dont consider the other phase noise ?
Could someone explain ?