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False path is specified when there is a signal propagating from 1 clock domain to another. If we don't specify false path here, the tool unnecessarily does this analysis and comes up with crazy timing figures.
Disable timing is specified when you don't want the tool to any analysis on a particular path e.g. from a top level clock which actually does not exist in practice.
Sarath, your explanation is not clear.
I'm still have confuse about them.
set_false_path is use for a pair of start & end point.
But set_disable just apply for 1 point in timing path.
Is it correct?
The false timing paths are paths that do not propagate logic level changes. This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis.
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