Hi,
I'm new to conformal lec and confused by some results.
as figure shows a RTL compared to synthesis netlist:
the golden has not-mapped DFF as 21131 while netlist has only 13 DFF not mapped. Does this mean the RTL has so many redundant logic to be optimized by synthesis tool? thanks.
What are the not-mappped DLATs are? Are they clock gating? Have you turn on clock gating remodelling? It is abnormal because there are often not much clock gating in RTL.