CONFORMAL LEC-EXTRA PORTS after MBIST INSERTION

[sabucheeru27@gmail.com]

Hi all,

I'm doing logical equivalence check between
1)RTL n MBIST inserted NETLIST
2)PLAIN NETLIST without MBIST n DFT stuffs vs MBIST inserted NETLIST
TEST_MODE is a top level pin of my design which when 0 makes the design in pure functional mode.My design is very complex and I'm moving with hierarchial comparison.So dpends on tool generated script.My issue is in the revised netlist there are many registers extra..which are the output ports of internal modules.So when i did

add pin constraints 0 TEST_MODE -revised
write hier dofile LEC.do -constraint -noexact -replace

since golden has no mbist cells many internal modules are skipped from hierarchial script(dofile).And when compared at the higher hierarchy of design it gave me many non equivalent points.So that the TEST_MODE 0 value cant be propagated.Please if anyone knows the solution please do reply

Please help,i'm in the critical stage of the project.

 

[englishdogg]

this is what i would suggest for you to perform your logic equivalence checking
1- RTL - DFT inserted netlist only (hierarchical)
2- DFT inserted netlist vs MBIST inserted netlist (flat)

In case (1) you only have to constrain the dft signal to ensure that your design is in functional mode this should be clean
in case (2) you will may still get extra ports since the MBIST doe snot exist in the golden side, which should be fine and you should be bale to get it clean

 

[sabucheeru27@gmail.com]

this is what i would suggest for you to perform your logic equivalence checking
1- RTL - DFT inserted netlist only (hierarchical)
2- DFT inserted netlist vs MBIST inserted netlist (flat)

In case (1) you only have to constrain the dft signal to ensure that your design is in functional mode this should be clean
in case (2) you will may still get extra ports since the MBIST doe snot exist in the golden side, which should be fine and you should be bale to get it clean

Hi Sir,

But the problem is when I tried to create an hierarchial script by constraining the DFT_SIGNAL(in my design TEST_MODE)and tried for automated script,it said some modules are skipped because of extra output ports.since those module has MBIST cells surrounding.Because of that constraint propagation is also not taking place.Please reply


Regards
Swaroop

 

[englishdogg]

@swaroop

If you execute RTL vs Netlist with MBIST this issue may arise again and again .. i would still suggest that you follow the two steps i mentioned above first
1- RTL - DFT inserted netlist only (hierarchical) --> this means no MBIST only DFT [basic scan chain connection]
2- DFT inserted netlist vs MBIST inserted netlist (flat)

 

[sabucheeru27@gmail.com]

@swaroop

If you execute RTL vs Netlist with MBIST this issue may arise again and again .. i would still suggest that you follow the two steps i mentioned above first
1- RTL - DFT inserted netlist only (hierarchical) --> this means no MBIST only DFT [basic scan chain connection]
2- DFT inserted netlist vs MBIST inserted netlist (flat)

Sir
I have solved the issue..actually in the mbist inserted netlist there was an extra tap system for mbist and dft stuffs..I constrained the main inputs of that tap..such as tdi tms trst (data_in,mode_select,reset respectively).Now the extra ports problem got over and successfully created the hier script..and when run it passed...

Thank you
SWAROOP

 

[englishdogg]

@swaroop

Great - ideally all DFT ports should be constrained during LEC execution.
But i am almost sure that the Extra ports will not lead to LEC failures - anyways good that you could resolve it

 

[sabucheeru27@gmail.com]

@swaroop

Great - ideally all DFT ports should be constrained during LEC execution.
But i am almost sure that the Extra ports will not lead to LEC failures - anyways good that you could resolve it

Thanks a lot Sir.....................