nohj_yar
Junior Member level 1
Hi all!
Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist."
My question is that what is the structure of the final SPICE netlist stated above? What is the difference between full chip netlist of an FPGA? Difference between full chip netlist of ASIC?
Thanks..
Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist."
My question is that what is the structure of the final SPICE netlist stated above? What is the difference between full chip netlist of an FPGA? Difference between full chip netlist of ASIC?
Thanks..