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Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC

harvie

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Hello. I am working on project based around Espressif ESP32 uC and Lattice ICE40 FPGA. FPGA will do some heavy lifting and handle several buses, while providing uC with preprocessed data over SPI.

So if i do some changes in uC firmware, i may as well need to update FPGA bitstream on flash and uC firmware on another flash. I wonder if i can completely ditch the flash storing FPGA configuration and configure the FPGA from uC firmware instead. So i will compile the FPGA bitstream as binary blob into the uC firmware and stream it to FPGA during uC boot.

I think it can reduce the BOM and make OTA firmware updates easier...

Is this common/reccomended way of doing things? Are there any downsides?
 

barry

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im not familiar with your uc. Can you read data from program flash? If so, then you can use it to store your FPGA bitstream.
 

harvie

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Use the "Slave SPI" mode.
Yes. I was hoping that uC in Slave SPI mode can pretend it's a flash IC to make things easy :)

BTW does the FPGA need the SPI to be online after the configuration was done? Can i reuse the SPI flash pins of FPGA in my HDL code? I already need to use slave SPI for communication between configured FPGA and uC, so it would be cool if i can configure the FPGA and then use the same Slave SPI bus to do my business after boot/configuration sequence.
 

barry

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Yes, you can use the SPI ports for your own nefarious needs after configuration. Just pay attention to what's attached to those ports.
 

FvM

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Yes. I was hoping that uC in Slave SPI mode can pretend it's a flash IC to make things easy.
"Slave SPI mode" in the configuration manual refers to operating the uC as SPI master and ICE40 as slave which is most likely the easier way.
 

ads-ee

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Yes. I was hoping that uC in Slave SPI mode can pretend it's a flash IC to make things easy :)
You should read the documentation. The FPGA is not the master when programming in SPI from a uC. The uC is the SPI master and programs the FPGA.

BTW does the FPGA need the SPI to be online after the configuration was done? Can i reuse the SPI flash pins of FPGA in my HDL code? I already need to use slave SPI for communication between configured FPGA and uC, so it would be cool if i can configure the FPGA and then use the same Slave SPI bus to do my business after boot/configuration sequence.
I doubt there is any way to access the SPI configuration pins in the FPGA fabric, but I can't check the documentation as I can't seem to download anything from Lattice's website right now all the PDF downloads stall after a MB or so downloaded.
 

harvie

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